Welcome to TiddlyWiki created by Jeremy Ruston, Copyright © 2007 UnaMesa Association
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<link rel='alternate' type='application/rss+xml' title='RSS' href='index.xml' />
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Background: #fff
Foreground: #000
PrimaryPale: #8cf
PrimaryLight: #18f
PrimaryMid: #04b
PrimaryDark: #014
SecondaryPale: #ffc
SecondaryLight: #fe8
SecondaryMid: #db4
SecondaryDark: #841
TertiaryPale: #eee
TertiaryLight: #ccc
TertiaryMid: #999
TertiaryDark: #666
Error: #f88
/*{{{*/
body {background:[[ColorPalette::Background]]; color:[[ColorPalette::Foreground]];}
a {color:[[ColorPalette::PrimaryMid]];}
a:hover {background-color:[[ColorPalette::PrimaryMid]]; color:[[ColorPalette::Background]];}
a img {border:0;}
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h1 {border-bottom:2px solid [[ColorPalette::TertiaryLight]];}
h2,h3 {border-bottom:1px solid [[ColorPalette::TertiaryLight]];}
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background:[[ColorPalette::TertiaryPale]];
border-left:1px solid [[ColorPalette::TertiaryLight]];
border-top:1px solid [[ColorPalette::TertiaryLight]];
border-right:1px solid [[ColorPalette::TertiaryLight]];
}
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.viewer pre {border:1px solid [[ColorPalette::SecondaryLight]]; background:[[ColorPalette::SecondaryPale]];}
.viewer code {color:[[ColorPalette::SecondaryDark]];}
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/*}}}*/
/*{{{*/
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body {font-size:.75em; font-family:arial,helvetica; margin:0; padding:0;}
h1,h2,h3,h4,h5,h6 {font-weight:bold; text-decoration:none;}
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dt {font-weight:bold;}
ol {list-style-type:decimal;}
ol ol {list-style-type:lower-alpha;}
ol ol ol {list-style-type:lower-roman;}
ol ol ol ol {list-style-type:decimal;}
ol ol ol ol ol {list-style-type:lower-alpha;}
ol ol ol ol ol ol {list-style-type:lower-roman;}
ol ol ol ol ol ol ol {list-style-type:decimal;}
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code.escaped {white-space:nowrap;}
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/* the 'a' is required for IE, otherwise it renders the whole tiddler in bold */
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#mainMenu .tiddlyLinkExisting,
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.header a:hover {background:transparent;}
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/*}}}*/
/***
StyleSheet for use when a translation requires any css style changes.
This StyleSheet can be used directly by languages such as Chinese, Japanese and Korean which need larger font sizes.
***/
/*{{{*/
body {font-size:0.8em;}
#sidebarOptions {font-size:1.05em;}
#sidebarOptions a {font-style:normal;}
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/*{{{*/
@media print {
#mainMenu, #sidebar, #messageArea, .toolbar, #backstageButton, #backstageArea {display: none ! important;}
#displayArea {margin: 1em 1em 0em 1em;}
/* Fixes a feature in Firefox 1.5.0.2 where print preview displays the noscript content */
noscript {display:none;}
}
/*}}}*/
<!--{{{-->
<div class='header' macro='gradient vert [[ColorPalette::PrimaryLight]] [[ColorPalette::PrimaryMid]]'>
<div class='headerShadow'>
<span class='siteTitle' refresh='content' tiddler='SiteTitle'></span>
<span class='siteSubtitle' refresh='content' tiddler='SiteSubtitle'></span>
</div>
<div class='headerForeground'>
<span class='siteTitle' refresh='content' tiddler='SiteTitle'></span>
<span class='siteSubtitle' refresh='content' tiddler='SiteSubtitle'></span>
</div>
</div>
<div id='mainMenu' refresh='content' tiddler='MainMenu'></div>
<div id='sidebar'>
<div id='sidebarOptions' refresh='content' tiddler='SideBarOptions'></div>
<div id='sidebarTabs' refresh='content' force='true' tiddler='SideBarTabs'></div>
</div>
<div id='displayArea'>
<div id='messageArea'></div>
<div id='tiddlerDisplay'></div>
</div>
<!--}}}-->
<!--{{{-->
<div class='toolbar' macro='toolbar [[ToolbarCommands::ViewToolbar]]'></div>
<div class='title' macro='view title'></div>
<div class='subtitle'><span macro='view modifier link'></span>, <span macro='view modified date'></span> (<span macro='message views.wikified.createdPrompt'></span> <span macro='view created date'></span>)</div>
<div class='tagging' macro='tagging'></div>
<div class='tagged' macro='tags'></div>
<div class='viewer' macro='view text wikified'></div>
<div class='tagClear'></div>
<!--}}}-->
<!--{{{-->
<div class='toolbar' macro='toolbar [[ToolbarCommands::EditToolbar]]'></div>
<div class='title' macro='view title'></div>
<div class='editor' macro='edit title'></div>
<div macro='annotations'></div>
<div class='editor' macro='edit text'></div>
<div class='editor' macro='edit tags'></div><div class='editorFooter'><span macro='message views.editor.tagPrompt'></span><span macro='tagChooser'></span></div>
<!--}}}-->
To get started with this blank TiddlyWiki, you'll need to modify the following tiddlers:
* SiteTitle & SiteSubtitle: The title and subtitle of the site, as shown above (after saving, they will also appear in the browser title bar)
* MainMenu: The menu (usually on the left)
* DefaultTiddlers: Contains the names of the tiddlers that you want to appear when the TiddlyWiki is opened
You'll also need to enter your username for signing your edits: <<option txtUserName>>
These InterfaceOptions for customising TiddlyWiki are saved in your browser
Your username for signing your edits. Write it as a WikiWord (eg JoeBloggs)
<<option txtUserName>>
<<option chkSaveBackups>> SaveBackups
<<option chkAutoSave>> AutoSave
<<option chkRegExpSearch>> RegExpSearch
<<option chkCaseSensitiveSearch>> CaseSensitiveSearch
<<option chkAnimate>> EnableAnimations
----
Also see AdvancedOptions
Five I/O ports are provided, the 'active' I/O port is read from the EEPROM on power up.
The currently active I/O port can be changed by writing to the Active IO [[Internal Register]]. To change the default
see the EEPROM must be updated, see the [[Device Configuration]] tiddler for details.
Five ports are provided for redundancy in the case where an IO pin is destroyed by accidental means, although the ability
to change the I/O port allows the 1 Pin Module to drive 5 separate devices/local busses at once. This could allow a manufacturing
test to initiate a test in one FPGA and verify test results in other devices and so on.
The I/O voltage used for the 5 1 Pin Interface [[I/O ports]] can set between 1.5V and 3.3V, it is supplied with I/O voltages of 1.5V, 1.8V, 2.5V and 3.3V defined.
The voltage is set with a PWM output with a range of (0x00 to 0xFF) into a simple low pass filter feeding the bottom end of a potential divider from 3.3V (see the schematics for details).
When set to 0x00 the output voltage is approximately 1.5V, when set to 0xFF the output is 3.3V, with a linear range between the two.
The PWM output can be changed at any time by writing to the PWM OP [[Internal Register]], although this won't change the default value.
When shipped the default is set to 3.3V
On Power up the [[Device Configuration]] EEPROM interface reads the currently set I/O voltage and writes this to the PWM ouptut. The [I/O
voltage]] default can be set to any voltage between 1.5V and 3.3V by writing the new value to the EEPROM.
A simple AT93C46 (128x8) EEPROM is provided to store device configuration information. On power up a simple state machine reads the first few addresses which hold the device configuration as follows...
| Address | Function |
| 0x00 | I/O Voltage Address (Also sets the I/O Voltage LED) |
| 0x01 | I/O Voltage 1 (3.3V) |
| 0x02 | I/O Voltage 2 (3.0V) |
| 0x03 | I/O Voltage 3 (2.5V) |
| 0x04 | I/O Voltage 4 (1.8V) |
| 0x10 | Active I/O Port |
The I/O Voltage Select is a pointer to address 0x01, 0x02, 0x03 or 0x04. The value in the set address is read and written to the [[I/O voltage]] setting output.
The Active I/O Port address is read and the relevent one of the [[I/O ports]] is selected.
The EEPROM can be read from and written to via the [[Internal Register]] read and write commands.
See the [[Setup_EEPROM_Defaults_01.zip|http://www.1pin-interface.com/download/Setup_EEPROM_Defaults_01.zip]] application for an example of how this interface is driven.
The following files are available for download.
''Drivers''
[[USB Drivers|http://www.1pin-interface.com/download/1pin_if_usb_drivers.zip]]
''Target FPGA core VHDL''
[[Target Core Logic|http://www.1pin-interface.com/download/one_pin_if_target_01.txt]]
''Example Software''
[[Quickstart_01.zip|http://www.1pin-interface.com/download/Quickstart_01.zip]]
[[Memory_Dump_01.zip|http://www.1pin-interface.com/download/Memory_Dump_01.zip]]
[[Voltage_Monitor_01.zip|http://www.1pin-interface.com/download/Voltage_Monitor_01.zip]]
[[FPGA_Update_01.zip|http://www.1pin-interface.com/download/FPGA_Update_01.zip]]
[[Setup_EEPROM_Defaults_01.zip|http://www.1pin-interface.com/download/Setup_EEPROM_Defaults_01.zip]]
[[VBA One Pin Module|http://www.1pin-interface.com/download/OnePinModule.txt]] as an example of how the Wr and Rd tranfers are driven
''Module Schematics''
[[1 Pin Module Schematics|http://www.1pin-interface.com/download/1_pin_interface_rev2.pdf]]
The interface is driven over the USB interface.
The first byte of any transaction has a 4 bit 'command' with the 4 most significant address bits.
The next byte is the least significant address bits.
The next two bytes contain the 16 bit write data if a write is being actioned.
| Action | Byte 1(7..4) | Byte 1(3..0) | Byte 2 | Byte 3 | Byte 4 | MS Rd Data Returned | LS Rd Data Returned |
| Register Write | 0xA | Addr(11..8) | Addr(7..0) | Data(15..8) | Data(7..0) | N/A | N/A |
| Register Read | 0x5 | Addr(11..8) | Addr(7..0) | N/A | N/A | Data(15..8) | Data(7..0) |
|Register Burst Write | 0xB | Addr(11..8) | Addr(7..0) | Burst Size |||
||||||||
| Internal Write | 0x01 | Dummy | Dummy | Dummy | Value(7..0) | N/A | N/A |
| Internal Read | 0x02 | Addr(11..8) Dummy | Addr(7..0) | Control_Bits(15..8) | Data(7..0) | N/A | N/A |
The 1 Pin Module FPGA image is stored in an M24P40 flash device, this can be updated over the USB interface to allow feature upgrades or custom application downloads.
A simple Excel app, ''"""FPGA_Update.xls"""'', is provided to do this, the EEPROM erase and re-programming should take less than 10 seconds.
If modifications to the 1 Pin Interface are made then the internal register interface should be kept unchanged and accessable if this is to be used for future image upgrades.
In the worst case scenario if an upgrade fails, the standard Altera Byteblaster header is available internally to restore a working image.
Only a single bi-directional FPGA pin is required to implement the interface. This allows a debug header to be implemented on most designs whether it is expected to be used or not.
The logic footprint depends slightly on the address range used, number of registers driven off the local bus and synthesis directives. A small interface implemented in an Altera Cyclone with no area optimisation uses 170 Logic Elements.
The following enhancements are planned.
* ''Burst Target Write and Read access''. The 1 Pin Interface is not meant to be a high data rate interface but the single word access can be pretty slow. Burst Write and Read functionality exists in the interface, we are working on example code to demonstrate how this can be driven.
* ''Target code in Verilog.'' We will release examples of the target code in Verilog as soon as we can bribe someone to write them for us.
Please let us know if there are any enhancements you think would be useful.
The 1 Pin Interface is easily driven from Excel, this can be quickly 'hacked' to test whatever is required and can be configured to generate test or calibration reports in a manufacturing application. (Any other language that can drive the FTDI DLLs could also be used to drive the interface, the FTDI webaiste for code examples).
The example host applications are delivered in Excel VBA.
Excel is almost universally available and the applications can be quickly changed to target new board testing. The examples are thoroughly commented to allow further development/adaptation easy.
*''Quickstart'' - This provides write access to an led output register in the Target FPGA and write and read access to a 'default' register.
*''~Voltage_Monitor'' - This was used to monitor the power rails on a new board that was being debugged. The FPGA resister values to be read are defined in the Sheet, the read results are also written to the sheet where they are compared to +/- 4% limits and conditionally highlighted. This allowed the status of the supplies to be checked with a quick glance. ''Note - The target reads are driven by a software timer.''
*''~Memory_Dump'' - This reads the contents of a 1024*16 memory and saves it in a binary file.
*''~FPGA_Update'' - This is used to update the FPGA firmware and is a good example of how the internal registers are driven. Note, this must be used with a valid *.rpd file or the FPGA will be corrupted and it will have to be re-programmed directly.
*''~Setup_EEPROM_Defaults'' - This is what's used to set the default 1 Pin Interface module configuration EEPROM values, this is another example of how internal registers are driven.
Download the examples here...
[[Quickstart_01.zip|http://www.1pin-interface.com/download/Quickstart_01.zip]]
[[Memory_Dump_01.zip|http://www.1pin-interface.com/download/Memory_Dump_01.zip]]
[[Voltage_Monitor_01.zip|http://www.1pin-interface.com/download/Voltage_Monitor_01.zip]]
[[FPGA_Update_01.zip|http://www.1pin-interface.com/download/FPGA_Update_01.zip]]
[[Setup_EEPROM_Defaults_01.zip|http://www.1pin-interface.com/download/Setup_EEPROM_Defaults_01.zip]]
Upon opening a spreadsheet clicking anywhere on the spreadsheet will launch the application. To view and edit the code behind the application hit """ALT-F11""" before clicking on the spreadsheet.
The easiest way of generating custom applications is to use the ''~OnePinWr()'' and ''~OnePinRd()'' functions that are provided in the ~OnePinInterface Module, these allow simple access to the target FPGA registers.
''Public Function """OnePinWr"""(addr As Integer, Data As Long)''
''Public Function """OnePinRd"""(addr As Integer) As Long''
The address is masked off to 12 bits, 16bits of data is transferred in both cases.
The [[Device Configuration]] registers in the 1 Pin Interface Module are accessed using the Internal Write and Read functions ''~IntOnrPinWr()'' and ''~IntOnePinRd()'' . These too use 12 address bits and 16 data bits.
''Public Function """IntOnePinWr"""(addr As Integer, Data As Long)''
''Public Function """IntOnePinRd"""(addr As Integer) As Long''
For those who do not have access to Excel, the VBA ~OnePinModule which holds the functions described above can be downloaded ([[Downloads]]). The code is simple and commented and is probably the easiest way of describing the trasfer protocols.
An FTDI 245R USB interface device is used to handle the USB interfacing. Any development language that can drive the """FTDI D2XX DLLs""" could be used to drive the 1 Pin Interface, ie C++ Builder,, C#, Delphi, Labview, Visual Basic, Visual C++, Java, Perl and Python. Please see the FTDI [[Code Examples|http://www.ftdichip.com/Projects/CodeExamples.htm]] web pages for details.
The 1 Pin Module ''Internal'' register map is as follows. This can be driven using the ''IntOnePinWr'' and ''IntOnePinRD'' functions, see the Set_Defaults.xls application for an example.
Note: The ASMI interface is the interface that allows the FPGA configuration prom to be driven. The EEPROM interface is where the Module default settings are stored.
| Address | Read/Write | Function |
| 0x00 | Rd | 1 Pin Module FPGA Revision |
| 0x02 | Wr | Set Interface Voltage PWM Value (reverts to default at next power up) |
| 0x04 | Rd | (15..8) - ModuleRevision |
| | | (7..0) - FPGA Revision |
| 0x20 | Wr | ASMI output enable |
| 0x21 | Wr | ASMI op code |
| | Rd | (15 downto 8) - ASMI op code (for verification) |
| | | (0) - ASMI tranfserring |
| 0x22 | Wr&Rd | ASMI address(23 .. 16) |
| 0x23 | Wr&Rd | ASMI address(15 .. 0) |
| 0x24 | Wr | ASMI write data(7 .. 0) |
| | Rd | (7 .. 0) ASMI read data |
| 0x25 | Wr | ASMI stop |
| 0x26 | Rd | (7 .. 0) - Debug signal to read what has been programmed |
| 0x30 | Wr&Rd | EEPROM address |
| 0x31 | Wr | EEPROM data(7 .. 0) |
| | Rd | (8) EEPROM Busy |
| | Rd | (7 .. 0 ) EEPROM read data |
| 0x32 | Wr | (1) - EEPROM Rd trigger |
| | | (0) - EEPROM Wr trigger |
| 0x40 | Wr | IO Channel Select (reverts to default at next power up) |
| | Rd | (7 .. 0) - The PWM value set at reset |
| Others | Wr&Rd | default_register(15 .. 0) |
The two sets of LEDs indicate...
* ''IO Voltage''
On power up a state machine reads the EEPROM to find the address that defines the IO voltage. This address is written to the IO voltage LED.
As shipped the colours indicate the IO voltages as follows...
| Green | 3.3 V |
| Red | 3.0 V |
| Orange | 2.5 V |
| Not lit | 1.8 V |
Note: Bear in mind the pre-defined values in the EEPROM can be changed so this table can be re-defined.
* ''Activity''
On power up the same state machine above also reads addess 0x10 to get the active IO channel, 1 - 5. The activity led flashes this number of times to indicate which channel is active, it then enters 'activity' mode....
When any activity occurs on the active IO port the activity LED flashes Green. If the 1 Pin Module state machine remains out of IDLE for more than 0.5 seconds the Target is considered not to have responded so the 1 Pin Module is hard reset, this places it back to IDLE awaiting a new command.
If a hard reset is being driven the activity led is driven RED for 0.5 seconds before the hard reset.
[[Overview]]
[[FPGA Resources]]
[[Host Software]]
[[Physical Interface]]
[[Target PCB Footprint]]
[[Target Local Bus]]
[[Quick Start Guide]]
[[1Pin I/O voltage]]
[[1Pin Active I/O port]]
[[Device Configuration]]
[[LEDs]]
[[USB Drivers]]
[[Downloads]]
[[Purchase]]
[[Schematics]]
[[FPGA Image Update]]
[[Future Enhancements]]
''The 1 Pin Interface is a simple, flexible, USB driven Test or Debug interface for """FPGAs""" and related Hardware''.
It allows easy access to internal FPGA control or status registers, memory contents etc via ''one FPGA pin''.
[img[1Pin Module|1Pin_IF.jpg]]
It is ideal for low level PCB or FPGA modular debug before supporting interfaces or software are ready. It is also ''ideal for manufacturing system test or calibration'' etc.
''It....''
* ''Uses minimal Target [[FPGA Resources]]'' (''1 pin'' and ''small logic footprint'' in the target device)
* ''Needs a minimal PCB footprint'', see [[Target PCB Footprint]]
* The ''[[Host Software]], driven from Excel, is simple to drive and configure'', and almost universally supported.(Other software languages can be used)
* ''Is self powered'' (from the USB interface)
* ''Is simple to use and implement''
* ''Is compact''
[img[Overview|Overview.jpg]]
A host PC drives the interface via the USB interface. Control and data information is sent to the 1 Pin module. This interprets the data from the host and sends it to the 'target' FPGA via a bi-directional serial interface. A small logic core in the FPGA de-serialises the stream and drives a simple 'local bus'. This drives read or write access to internal registers in the target device. If a read is being actioned the returned data is sent serially on the bi-directional interface, received by the interface and sent back to the host.
* The [[I/O voltage]] can be varied from 1.5V to 3.3V (Units ship with values for 3.3V, 3.0V, 2.5V and 1.8V predefined).
* There are 5 [[I/O ports]] for redundancy, or driving several devices at once (the 'active' output can be changed on the fly)
* The serial Interface speed is set to 10Mbps, different [[Target Core Clock Rates]] can be used with a simple Generic divider.
* The [[Device Configuration]] (I/O Voltage and active I/O port used) is held in local EEPROM. This is easily modified.
* The [[FPGA image]] can be updated via the USB interface for functional upgrades etc.
''Note:'' The 1 Pin Interface is not designed to compete with Chipscope or Signaltap type products which operate at a very low 'logic analyser' level on individual signals. The 1 Pin Interface is designed to operate at a much higher functional level driving control and reading status registers.
The best way of checking out how simple the 1 Pin Interface is to use is to run through the [[Quick Start Guide]].
!Example Applications
* The board under test below is part of a much bigger system and is driven via a serial interface. The 1 Pin Interface is being used to drive a set of ADC control outputs for hardware characterisation before the rest of the system was available for test.
[img[1Pin Module In Use|1pin_if_in_use.jpg]]
* In another project the logic for an on screen display module had been completed, this was to be driven via an SPI interface from the client's hardware. In order to test the functionality of the logic the 1 Pin Interace was used to drive Horizontal, Vertical offsets, Pixel widths and heights etc. This allowed full debug before receiving the client's hardware. The Excel VBA interface to drive this was very easily and quickly 'hacked' together and is shown here..
[img[Easy Register Access|app2.jpg]]
!NOTE
This website is a [[TiddlyWiki|http://www.tiddlywiki.com/]] and is a single file. This can be saved to your local disc to allow access to the documentation within when off-line
The physical interface to the target device is two wires, the bi-directional data line and a GND.
The IO voltage can be anywhere between 3.3V and 1.5V, the unit ships with values set for 3.3V, 3.0V, 2.5V and 1.8V.
The 1 Pin Module has been tested operating at a lower output voltage than the target device. However the IO lines have protection diodes to GND and 'VCC' internally so the IO voltage should be set to the same as the target logic or the protection diodes to VCC will be switched on, possibly damaging the target output.
See [[Device Configuration]] for details of setting the IO Voltage.
!Connection
The connection to the 1 Pin Module can be a two pin header or a 10 pin IDC header, the units are production tested with a 10 way IDC header and 10 way ribbon cable that is over 1 meter long to another 10 way IDC header.
In use it is expected that each target will be accessed with a 2 way header, but this is flexible. The length of the interface should be kept reasonably short (20 cm?) to maximise signal integrity.
The introductory price for the 1 Pin Module is set at ''GBP £95.00'' (+ VAT for EU purchasers), this equates to around ''USD $145''.
''To purchase a 1 Pin Interface module please follow'' [[this link|http://www.nialstewartdevelopments.co.uk/products.htm]]
There are 9 simple steps to getting the 1 Pin interface running from scratch with a 'light some leds' demo. You'll need an FPGA board with LEDs and an IO pin you can connect to with ideally an adjacent ground.
1) Download the 1 Pin [[USB Drivers]]. Plug the 1 Pin Interface into your computer and point it to where the drivers are (standard USB device install).
2) Instantiate the following signals in the Target FPGA
{{{
-- Debug One pin local bus signals
signal lb_address : std_logic_vector(11 downto 0);
signal lb_d_out : std_logic_vector(15 downto 0);
signal lb_d_in : std_logic_vector(15 downto 0);
signal lb_wr : std_logic;
signal lb_rd : std_logic;
signal lb_din_valid : std_logic;
signal leds : std_logic_vector(7 downto 0);
signal default_reg : std_logic_vector(15 downto 0);
}}}
2a) Declare the 1 Pin component (if using medieval tools) .
3) Download the Target Core ([[Downloads]]) and add it to your project.
4) Instantiate the Target Core Entity, with a Write and read processes.
{{{
-------------------------------------------------------------------------------
-- 1 Pin Interface
-------------------------------------------------------------------------------
target:entity work.one_pin_if_target
generic map(
serial_clk_divisor => 8) -- in integer range 1 to 10 := 8
port map(
clk => clk , -- in std_logic; -- 80 MHz
rst => rst , -- in std_logic; -- '1' = reset
one_pin_if => one_pin_if , -- inout std_logic;
lb_address => lb_address , -- out std_logic_vector(11 downto 0);
lb_d_out => lb_d_out , -- out std_logic_vector(15 downto 0);
lb_d_in => lb_d_in , -- in std_logic_vector(15 downto 0);
lb_wr => lb_wr , -- out std_logic;
lb_rd => lb_rd , -- out std_logic;
lb_din_valid => lb_din_valid -- in std_logic
);
-- Write process
process(clk,rst)
begin
if(rst = '1') then
leds <= (others => '0');
default_reg <= x"BEEF";
elsif(rising_edge(clk)) then
if(lb_wr = '1') then
case lb_address(11 downto 0) is
when x"001" =>
leds <= lb_d_out(7 downto 0);
when x"002" =>
default_reg <= lb_d_out;
when others =>
null;
end case;
end if;
end if;
end process;
-- Read Process
process(clk,rst)
begin
if(rst = '1') then
lb_din_valid <= '0';
lb_d_in <= (others => '0');
elsif(rising_edge(clk)) then
if(lb_rd = '1') then
lb_din_valid <= '1';
case lb_address is
when x"004" =>
lb_d_in(7 downto 0) <= default_reg;
when OTHERS =>
null;
end case;
end if;
end if;
end process;
}}}
5) Connect up to the board LEDs
{{{
board_leds <= leds;
}}}
6) Set the serial clock divider in the 1 Pin Target Interface Generic map to System_clock/10MHz. The following would be used with a system clock to 50 MHz.
{{{
serial_clk_divisor => 5) -- in integer range 1 to 10 := 8
}}}
7) Build and configure the target FPGA.
8) Connect to 1 Pin output pin.
9) Download, unzip and run the ''Quickstart_01.xls'' application ([[Downloads]]) and flash your leds / access the internal register.
The schematics for the 1 Pin Module are available in [[Downloads]]
Flexible FPGA Debug Interface
http://www.1Pin-Interface.com
The serial interface bit rate is set to 10Mbps.
An integer generic, ''serial_clk_divisor'', in the ''Target Core'' port map allows different target core clock rates to be used with the 1 Pin Interface.
The core runs, and drives register accesses at the system clock rate, the Generic sets the interface speed where...
''serial_clk_divisor'' = System Clock Rate / 10
See the ''one_pin_if_target.vhd'' file for details.
Registers in the Target FPGA are accessed via the 1 Pin Local Bus, this provides 16 bit access to 1024 addresses as follows...
{{{
lb_address => lb_address , -- out std_logic_vector(11 downto 0);
lb_d_out => lb_d_out , -- out std_logic_vector(15 downto 0);
lb_d_in => lb_d_in , -- in std_logic_vector(15 downto 0);
lb_wr => lb_wr , -- out std_logic;
lb_rd => lb_rd , -- out std_logic;
lb_din_valid => lb_din_valid -- in std_logic
}}}
The Write (lb_wr) strobe is active high for one 'system' clock cycle.
The Read (lb_rd) strobe is active high for one system clock cycle. The interface state machine then waits until lb_din_valid is active high before it reads the data in. This allows for delays where the read data isn't returned immediately (registered """RAMs""" etc). In most instances where the read data is returned immediately this can be returned as...
{{{
lb_din_valid <= lb_rd;
}}}
..in a synchronous process (see the Quick Start code for an example).
The only requirement of a target board is that a reasonably direct connection can be made to an FPGA IO pin and a GND.
The 1 Pin Module pulls the data lines weakly low (with a 47K resistor) so no pull down is required on the target board, ie it can be used with any evaluation board.
If the 1 Pin interface is to be permanently enabled in the target logic, say for manufacturing test or analogue input or output calibration, a pull down resistor of approximately 4K7 Ohms should be provided.
For fast manufacturing access two pads could be provided on the bottom of the board to allow bed of nails access to the 1 Pin Target logic.
For access on a third part eval board all that is needed is connection to an FPGA pin and GND.
Only Windows drivers are available, see [[Downloads]]
Download the unzip the drivers to your computer.
When the 1 Pin Interface is plugged in for the first time select the driver directory and hit OK.
A warning about the driver not having passed Windows Logo testing will be displayed, select 'Continue Anyway' and the drivers should be installed.
''Note:'' Like all USB devices if the 1 Pin Interface is plugged into a different USB port on your computer the driver will have to be re-installed so it makes sense to chose the port which will be used most often initially.